The growth of battery-powered mobile and wearable devices has increased the importance of low power operation and cost in system-on-chip (SoC) design. Peripheral assist circuits that enhance process window for Static Random Access Memory (SRAM) operation at low voltage are an increasingly important area of focus for continued SRAM scaling in face of increasing process variability.
Transient voltage collapse (TVC) write assist circuits have been used to significantly enhance the operating voltage window for the highest density SRAM bit-cells. However, the most significant drawback of the TVC write assist scheme is the elevated active write power dissipation associated with the switching of the highly capacitive memory power supply, SRAMVCC supply, and discharging and charging back up high (or ‘1’) bit-cell storage nodes of the entire memory sector under access (divided by the column multiplexer (CM) factor). Furthermore, the inability to power un-accessed portions of active memory arrays at the lowest retention voltage state further limits reduction in the leakage power dissipation of active SRAM macros (e.g., SRAM banks) in a design.